Digital VLSI Design with Verilog

This hands-on program presents to the students the design of digital integrated circuits using the Verilog digital design language as described in IEEE Standard 1364-2001. By a balanced mixture of lectures and labs the students are introduced to language constructs in a progressively more complex project environment. During the program students will become familiar with the use of the Synopsys Design Compiler to synthesize gate-level netlists from behavioral RTL and structural Verilog code. The synthesis constraints most useful for area and speed optimization are emphasized. Almost all work is done in the synthesizable subset of the language logic simulation is treated as an occasional verification method. Other topics include design partitioning hierarchy decomposition safe coding styles assertion-based verification and design for test. New program starts Jan 12 2016. This program is offering on WebEx. For more information please contact Silicon Valley Polytechnic Institute info(at) or call 408-436-3000.



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