Urgent openings for design engineers in chennai (Chennai)

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Urgent openings for design engineers in chennai

Job DescriptionGood knowledge on Verilog. Language proficiency is expected to be very high.SV exposure is a value addition.Good knowledge in circuit design basicsExpert in integrating processor based SOC. Either the target could be ASIC or FPGA.Exposure to Linting Formal verification is value addition.Simulation (RTL GLS) is must.Experience0-3 YearsLocationChennaisalary18 k -22k incentives DA HRA extratimingday shiftif you are interested calldevi hr9176074708

04-03-2024 INDIA, Chennai
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